`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/22 17:04:39
// Design Name: 
// Module Name: pc_reg
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "defines.vh"

module pc_reg(
    input   logic               clk, res,
    input   logic               en,
    input   logic               clr,
    input   logic [31: 0]       flush_pc,
    input   logic [31: 0]       pc_next,
    output  logic [31: 0]       pc,
    output  logic [`EXCS_BUS]   excs    //exceptions
    );

    always @(posedge clk, posedge res) begin
        if(res) begin
            pc <= 32'hbfc0_0000;    //need to be change to 32'hBFC0_0000.
        end
        else if(clr) begin 
            pc <= flush_pc;
        end
        else if (en) begin
            pc <= pc_next;
        end
    end

    logic exc_i_ade;
    assign exc_i_ade = (pc[1:0] != 2'b00);

    always_comb begin
        excs             = 0;
        excs[`EXC_I_ADE] = exc_i_ade;
    end

endmodule
